PP1_STATUS (GPU) Register Description
| Register Name | PP1_STATUS |
|---|---|
| Offset Address | 0x000000B008 |
| Absolute Address | 0x00FD4BB008 (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Pixel Processor Status Register |
PP1_STATUS (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:8 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
| CLK_OVERRIDE | 7 | rwNormal read/write | 0x0 | Shows that the block level clock gates have been disabled. This bit is set by the CLK_OVERRIDE command in the CTRL_MGMT Register. When this bit is set, all the architectural clock gates in the design are overridden so all clocks are always active. |
| INTERRUPT_ASSERTED | 6 | rwNormal read/write | 0x0 | Shows the current status of the interrupt request line of the pixel processor. |
| WRITE_BOUNDARY_ERROR | 5 | rwNormal read/write | 0x0 | Show that the pixel processor attempted to write outside the write boundary set by the WRITE_BOUNDARY registers. |
| BUS_STOPPED | 4 | rwNormal read/write | 0x0 | Shows that the master bus interface of the pixel processor has been stopped because of a STOP_BUS command or a performance counter limit event. The bus interface can be restarted by using the START_BUS command. |
| BUS_ERROR | 3 | rwNormal read/write | 0x0 | A bus transaction has ended with error. The pixel processor has been stopped and has to be reset before rendering can be started again. |
| HANG | 2 | rwNormal read/write | 0x0 | Watchdog timer limit reached. This state can also be triggered under normal rendering if you are running a shader where it is near to a never-ending inner loop. From the software perspective, you can ignore this state, because this is merely a hint from the HW that something might be wrong. The SW then decides to either reset the processor, or continue to let it run. |
| TILE_STOPPED | 1 | rwNormal read/write | 0x0 | Rendering of the current tile has been completed as if it was the last tile of the frame. Indicates that an END_AFTER_TILE command has been issued. |
| RENDERING_ACTIVE | 0 | rwNormal read/write | 0x0 | The pixel processor is currently active rendering. |