Counter_Control_2 (TTC) Register Description
| Register Name | Counter_Control_2 |
|---|---|
| Offset Address | 0x0000000010 |
| Absolute Address |
0x00FF110010 (TTC0) 0x00FF120010 (TTC1) 0x00FF130010 (TTC2) 0x00FF140010 (TTC3) |
| Width | 7 |
| Type | rwNormal read/write |
| Reset Value | 0x00000021 |
| Description | Operational mode and reset |
Counter_Control_2 (TTC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Wave_pol | 6 | rwNormal read/write | 0x0 | Waveform polarity: When this bit is high, the waveform output goes from high to low on Match_1 interrupt and returns high on overflow or interval interrupt; when low, the waveform goes from low to high on Match_1 interrupt and returns low on overflow or interval interrupt. |
| Wave_en | 5 | rwNormal read/write | 0x1 | Output waveform enable, active low. |
| RST | 4 | rwNormal read/write | 0x0 | Setting this bit high resets the counter value and restarts counting; the RST bit is automatically cleared on restart. |
| Match | 3 | rwNormal read/write | 0x0 | Register Match mode: when Match is set, an interrupt is generated when the count value matches one of the three match registers and the corresponding bit is set in the Interrupt Enable register. |
| DEC | 2 | rwNormal read/write | 0x0 | Decrement: when this bit is high the counter counts down. |
| INT | 1 | rwNormal read/write | 0x0 | When this bit is high, the timer is in Interval Mode, and the counter generates interrupts at regular intervals; when low, the timer is in overflow mode. |
| DIS | 0 | rwNormal read/write | 0x1 | Disable counter: when this bit is high, the counter is stopped, holding its last value until reset, restarted or enabled again. |