| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31 | razRead as zero | 0x0 | reserved |
| rd_fifo1_sample_present | 30:24 | roRead-only | 0x0 | No. of samples present in 2nd read latency measurement FIFO. This represent the no. of outstanding transactions at the end of the configured timing window. This is for debug purpose. |
| Reserved | 23 | razRead as zero | 0x0 | reserved |
| rd_fifo0_sample_present | 22:16 | roRead-only | 0x0 | No. of samples present in 1st read latency measurement FIFO. This represent the no. of outstanding transactions at the end of the configured timing window. This is for debug purpose. |
| Reserved | 15 | razRead as zero | 0x0 | reserved |
| wr_fifo1_sample_present | 14:8 | roRead-only | 0x0 | No. of samples present in 2nd write latency measurement FIFO. This represent the no. of outstanding transactions at the end of the configured timing window. This is for debug purpose. |
| Reserved | 7 | razRead as zero | 0x0 | reserved |
| wr_fifo0_sample_present | 6:0 | roRead-only | 0x0 | No. of samples present in 1st write latency measurement FIFO. This represent the no. of outstanding transactions at the end of the configured timing window. This is for debug purpose. |