ATTR_72 (PCIE_ATTRIB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ATTR_72 (PCIE_ATTRIB) Register Description

Register NameATTR_72
Offset Address0x0000000120
Absolute Address 0x00FD480120 (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x00000001
DescriptionATTR_72

This register should only be written to during reset of the PCIe block

ATTR_72 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_rbar_cap_sup415:0rwNormal read/write0x1BAR Size Supported vector for Resizable BAR Capability Register(4). Bits[3:0] and [31:24] sould always be driven to 0.