cfg (EFUSE) Register Description
| Register Name | cfg |
|---|---|
| Offset Address | 0x0000000004 |
| Absolute Address | 0x00FFCC0004 (EFUSE) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Configuration |
cfg (EFUSE) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| slverr_enable | 5 | rwNormal read/write | 0x0 | By default, invalid address requests are ignored. However, a maskable interrupt exsists. By enabling this slverr_enable invalid address requests cause a slverr to occur. Enable/Disable SLVERR during address decode failure. 0: SLVERR is disabled. For request address: Writes are ignored. Read returns 0. 1: SLVERR is enabled. For requestes address, SLVERR is asserted. Writes are ignored. Read returns 0. |
| margin_rd | 3:2 | rwNormal read/write | 0x0 | eFuse read margin control 00: Normal Read 01: Margin 1 Read 10: Margin 2 Read 11: Reserved |
| pgm_en | 1 | rwNormal read/write | 0x0 | eFuse PS control, enabled programming if set |
| efuse_clk_sel | 0 | rwNormal read/write | 0x0 | Selects the source of the eFuse clock. The PS_REF_CLK MUST be used when programming the eFuse and a very accurate clock is required (+/- 5%). The default value of the timing parameters are set for the Internal ring oscillator and must be changed when the clock source is changed. 0: Internal Ring Oscillator 1: PS_REF_CLK |