GICP1_IRQ_ENABLE (LPD_SLCR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GICP1_IRQ_ENABLE (LPD_SLCR) Register Description

Register NameGICP1_IRQ_ENABLE
Offset Address0x000000801C
Absolute Address 0x00FF41801C (LPD_SLCR)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionInterrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)

GICP1_IRQ_ENABLE (LPD_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
src3131woWrite-only0x0Gigabit Ethernet3 interrupt
src3030woWrite-only0x0Gigabit Ethernet2 wakeup interrupt
src2929woWrite-only0x0Gigabit Ethernet2 interrupt
src2828woWrite-only0x0Gigabit Ethernet1 wakeup interrupt
src2727woWrite-only0x0Gigabit Ethernet1 interrupt
src2626woWrite-only0x0Ethernet0 wakeup interrupt
src2525woWrite-only0x0Ethernet0 interrupt
src2424woWrite-only0x0AMS interrupt
src2323woWrite-only0x0AIB AXI interrupt
src2222woWrite-only0x0ATB interrupt
src2121woWrite-only0x0WDT in the CSUPMU: This is Edge trigger interrupt and Interrupt pulse width case be prograbble window from 40ns to 320ns. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for.
src2020woWrite-only0x0WDT in the LPD (IOU). This is Edge trigger interrupt and Interrupt pulse width case be prograbble window from 40ns to 320ns. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for.
src1919woWrite-only0x0SDIO1 wake interrupt
src1818woWrite-only0x0SDIO0 wake interrupt
src1717woWrite-only0x0SDIO1 interrupt
src1616woWrite-only0x0SDIO0 interrupt
src1515woWrite-only0x0Triple Time Counter3
src1414woWrite-only0x0Triple Time Counter3
src1313woWrite-only0x0Triple Time Counter3
src1212woWrite-only0x0Triple Timer Counter2
src1111woWrite-only0x0Triple Timer Counter2
src1010woWrite-only0x0Triple Timer Counter2
src9 9woWrite-only0x0Triple Timer counter1
src8 8woWrite-only0x0Triple Timer counter1
src7 7woWrite-only0x0Triple Timer counter1
src6 6woWrite-only0x0Triple Timer counter0
src5 5woWrite-only0x0Triple Timer counter0
src4 4woWrite-only0x0Triple Timer counter0
src3 3woWrite-only0x0APU_IPI0: OR of all of IPIs targeted to APU CPU
src2 2woWrite-only0x0RPU_IPI1: OR of all of IPIs targeted to RPU CPU1
src1 1woWrite-only0x0RPU_IPI0: OR of all of IPIs targeted to RPU CPU0
src0 0woWrite-only0x0PL_IPI3: OR of all of IPIs targeted to RPU PL3