PP0_INT_STATUS (GPU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PP0_INT_STATUS (GPU) Register Description

Register NamePP0_INT_STATUS
Offset Address0x000000902C
Absolute Address 0x00FD4B902C (GPU)
Width32
TyperwNormal read/write
Reset Value0x00001000
DescriptionInterrupt Status Register

PP0_INT_STATUS (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:13rwNormal read/write0x0Reserved, write as zero, read undefined.
RESET_COMPLETED12rwNormal read/write0x1Enabled when an interrupt of this type.
CALL_STACK_OVERFLOW11rwNormal read/write0x0Enabled when an interrupt of this type.
CALL_STACK_UNDERFLOW10rwNormal read/write0x0Enabled when an interrupt of this type.
INVALID_PLIST_COMMAND 9rwNormal read/write0x0Enabled when an interrupt of this type.
WRITE_BOUNDARY_ERROR 8rwNormal read/write0x0Enabled when an interrupt of this type.
CNT_1_LIMIT 7rwNormal read/write0x0Enabled when an interrupt of this type.
CNT_0_LIMIT 6rwNormal read/write0x0Enabled when an interrupt of this type.
BUS_STOP 5rwNormal read/write0x0Enabled when an interrupt of this type.
BUS_ERROR 4rwNormal read/write0x0Enabled when an interrupt of this type.
FORCE_HANG 3rwNormal read/write0x0Enabled when an interrupt of this type.
HANG 2rwNormal read/write0x0Enabled when an interrupt of this type.
END_OF_TILE 1rwNormal read/write0x0Enabled when an interrupt of this type.
END_OF_FRAME 0rwNormal read/write0x0Enabled when an interrupt of this type.