REQ_PWRDWN_STATUS (PMU_GLOBAL) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

REQ_PWRDWN_STATUS (PMU_GLOBAL) Register Description

Register NameREQ_PWRDWN_STATUS
Offset Address0x0000000210
Absolute Address 0x00FFD80210 (PMU_GLOBAL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionPower-down or RAM Retention Request; Interrupt Status and Clear.

The software can read the status and clear power-down requests: READ: 0: no request. 1: unit power-up requested. WRITE: 0: no effect. 1: clear bit to 0. Note: If a Status bit is 1 and its Mask is 0, then the interrupt signal is active to the interrupt controllers. The software requests a power-down using the REQ_PWRDWN_TRIG register.

REQ_PWRDWN_STATUS (PMU_GLOBAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:24roRead-only0x0reserved
PL23wtcReadable, write a 1 to clear0x0Programmable Logic, PL. Controlled by external FET via MIO pin. This optional control uses MIO [32] and is equivalent to PMU signal [6].
FP22wtcReadable, write a 1 to clear0x0Full-power Domain, FPD. Controlled by external FET via MIO pin. This optional control uses MIO [31] and is equivalent to PMU signal [5].
USB121wtcReadable, write a 1 to clear0x0USB controller 1.
USB020wtcReadable, write a 1 to clear0x0USB controller 0.
OCM_Bank319wtcReadable, write a 1 to clear0x0OCM Bank 3.
OCM_Bank218wtcReadable, write a 1 to clear0x0OCM Bank 2.
OCM_Bank117wtcReadable, write a 1 to clear0x0OCM Bank 1.
OCM_Bank016wtcReadable, write a 1 to clear0x0OCM Bank 0.
TCM1B15wtcReadable, write a 1 to clear0x0RPU core 1, TCM_B.
TCM1A14wtcReadable, write a 1 to clear0x0RPU core 1, TCM_A.
TCM0B13wtcReadable, write a 1 to clear0x0RPU core 0, TCM_B.
TCM0A12wtcReadable, write a 1 to clear0x0RPU core 0, TCM_A.
Reserved11roRead-only0x0reserved
RPU10wtcReadable, write a 1 to clear0x0RPU processors.
Reserved 9roRead-only0x0reserved
Reserved 8roRead-only0x0reserved
L2_Bank0 7wtcReadable, write a 1 to clear0x0APU L2 Cache.
Reserved 6roRead-only0x0reserved
PP1 5wtcReadable, write a 1 to clear0x0GPU Pixel Processor 1.
PP0 4wtcReadable, write a 1 to clear0x0GPU Pixel Processor 0.
ACPU3 3wtcReadable, write a 1 to clear0x0APU core 3.
ACPU2 2wtcReadable, write a 1 to clear0x0APU core 2.
ACPU1 1wtcReadable, write a 1 to clear0x0APU core 1.
ACPU0 0wtcReadable, write a 1 to clear0x0APU core 0.