L3_TXPMA_ST_0 (SERDES) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

L3_TXPMA_ST_0 (SERDES) Register Description

Register NameL3_TXPMA_ST_0
Offset Address0x000000CB00
Absolute Address 0x00FD40CB00 (SERDES)
Width32
TyperoRead-only
Reset Value0x00000001
DescriptionRegister value is generated by Vivado PCW.

L3_TXPMA_ST_0 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TXPMA_ST_0_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
TX_phy_mode 7:4roRead-only0x0Value generated by PCW.
TX_phy_gear 3:0roRead-only0x1Value generated by PCW.