PGCR5 (DDR_PHY) Register Description
| Register Name | PGCR5 |
|---|---|
| Offset Address | 0x0000000024 |
| Absolute Address | 0x00FD080024 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x01010000 |
| Description | PHY General Configuration Register 5 |
PGCR5 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| FRQBT | 31:24 | rwNormal read/write | 0x1 | Frequency B Ratio Term: This 8-bit value represents the value of the term associated with the secondary operating frequency. The secondary operating frequency is associated with the fields in this register DDLPGRW/DDLPGACT with a setting of 1b1. Valid values are from 1 to 255. Note: This register field is available only when DWC_SHADOW_REGISTERS is defined |
| FRQAT | 23:16 | rwNormal read/write | 0x1 | Frequency A Ratio Term: This 8-bit value represents the value of the term associated with the primary operating frequency. The primary operating frequency is associated with the fields in this register DDLPGRW/DDLPGACT with a setting of 1b0. Valid values are from 1 to 255. |
| DISCNPERIOD | 15:8 | rwNormal read/write | 0x0 | DFI Disconnect Time Period: Disconnect timer programmable value |
| VREF_RBCTRL | 7:4 | rwNormal read/write | 0x0 | Receiver bias core side control |
| Reserved | 3 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| DXREFISELRANGE | 2 | rwNormal read/write | 0x0 | Internal VREF generator REFSEL range select |
| DDLPGACT | 1 | rwNormal read/write | 0x0 | DDL Page Read Write select: Specifies the page of registers being applied to the PHY for mission mode operation. This bit also determines the page of registers to be updated during training execution. The registers associated with DDLPGACT = 1b0 must be used for the primary operating frequency. The registers associated with DDLPGACT = 1b1 can then be utilized for a second operating frequency. Note: This register field is available only when DWC_SHADOW_REGISTERS is defined |
| DDLPGRW | 0 | rwNormal read/write | 0x0 | DDL Page Read Write select: Specifies the page of DDL registers accessible through the APB configuration port. A DDLPGRW value of 1b0 accesses DDL register values associated with frequency setting (A). A DDLPGRW value of 1b1 accesses DDL register values associated with frequency setting (B). The following DDL registers or fields each have two registers addressed at the given PUB address values: ACLCDLR0, ACMDLR0, ACMDLR1, DXnLCDLR0, DXnLCDLR1, DXnLCDLR2, DXnLCDLR3, DXnLCDLR4, DXnLCDLR5, DXnMDLR0, DXnMDLR1, DXnGTR0, DXnGTR1, DXnGSR0.WLPRD, DXnGSR0.GDQSPRD, DXnGSR2.GDQSPRD, DXnGCR0.RDDLY Note: This register field is available only when DWC_SHADOW_REGISTERS is defined |