INT_DIS_0 (GPIO) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

INT_DIS_0 (GPIO) Register Description

Register NameINT_DIS_0
Offset Address0x0000000214
Absolute Address 0x00FF0A0214 (GPIO)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Disable/Mask (GPIO Bank0, MIO)

This register is used to disable or mask a GPIO input for use as an interrupt source. Writing a 1 to any bit of this register disables/masks that signal for interrupts. Reading from this register returns an unpredictable value. This register controls bank0, which corresponds to MIO[25:0].

INT_DIS_0 (GPIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:26razRead as zero0x0Not used, read back as zero
INT_DISABLE_025:0woWrite-only0x0Interrupt disable
0: no change
1: set interrupt mask
Each bit configures the corresponding pin within the 26-bit bank