Mode (UART) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Mode (UART) Register Description

Register NameMode
Offset Address0x0000000004
Absolute Address 0x00FF000004 (UART0)
0x00FF010004 (UART1)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionUART Mode Register

The UART Mode register defines the setup of the data format to be transmitted or received. If this register is modified during transmission or reception, data validity cannot be guaranteed.

Mode (UART) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:14roRead-only0x0Reserved, read as zero, ignored on write.
WSIZE13:12rwNormal read/write0x0Configure the size of FIFO access from the APB
00: One or two bytes written to TX FIFO or read from RX FIFO. If byte_sel is high then one byte is written or read, if byte_sel is low then two bytes are written or read (default legacy mode)
01: One byte is always written or read from FIFOs, regardless of whether byte_sel is active
10: Two bytes are always written or read from FIFOs, regardless of whether byte_sel is active
11: Four bytes are always written or read from FIFOs regardless of byte_sel (assuming configured width of APB supports four bytes)
CHMODE 9:8rwNormal read/write0x0Channel mode: Defines the mode of operation of the UART.
00: normal
01: automatic echo
10: local loopback
11: remote loopback
0:
LPD_LSBUS_CLK clock.
1: a user-defined clock
0: Default UART mode
1: Enable IrDA mode
NBSTOP 7:6rwNormal read/write0x0Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit.
00: 1 stop bit
01: 1.5 stop bits
10: 2 stop bits
11: reserved
PAR 5:3rwNormal read/write0x0Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit.
000: even parity
001: odd parity
010: forced to 0 parity (space)
011: forced to 1 parity (mark)
1xx: no parity
CHRL 2:1rwNormal read/write0x0Character length select: Defines the number of bits in each character.
11: 6 bits
10: 7 bits
0x: 8 bits
CLKS 0rwNormal read/write0x0Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock.
0: clock source is UART_REF_CLK
1: clock source is UART_REF_CLK/8