CTR (R5_DBG_1) Register - CTR (R5_DBG_1) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2025-06-20
Revision: 1.11

CTR (R5_DBG_1) Register Description

Register Name	CTR
Offset Address	0x0000000D04
Absolute Address	0x00FEBF2D04 (CORESIGHT_R5_DBG_1)
Width	32
Type	roRead-only
Reset Value	0x8003C003
Description	Cache Type Register

CTR (R5_DBG_1) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
Reserved	31:28	roRead-only	0x8	Always b1000.
CWG	27:24	roRead-only	0x0	CWG Cache Write-back Granule. 0x0= No information provided. See maximum cache line size in c0, Cache Size ID Registeron page 4-34.
ERG	23:20	roRead-only	0x0	ERG Exclusives Reservation Granule. 0x0= No information provided.
DMinLine	19:16	roRead-only	0x3	DMinLine Indicates log2 of the number of words in the smallest cache line of the data and unified caches controlled by the processor: 0x3= Eight words in an L1 data cache line.
Reserved	15:14	roRead-only	0x3	Always 0x3.
Reserved	13:4	roRead-only	0x0	Always 0x000.
IMinLine	3:0	roRead-only	0x3	IMinLine Indicates log2 of the number of words in the smallest cache line of the instruction caches controlled by the processor: 0x3- Eight words in an L1 instruction cache line.