Baud_rate_gen (UART) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Baud_rate_gen (UART) Register Description

Register NameBaud_rate_gen
Offset Address0x0000000018
Absolute Address 0x00FF000018 (UART0)
0x00FF010018 (UART1)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x0000028B
DescriptionBaud Rate Generator Register.

The read/write baud rate generator control register controls the amount by which to divide sel_clk to generate the bit rate clock enable, baud_sample.

Baud_rate_gen (UART) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16roRead-only0x0Reserved, read as zero, ignored on write.
CD15:0rwNormal read/write0x28BBaud Rate Clock Divisor Value:
0: Disables baud_sample
1: Clock divisor bypass (baud_sample = sel_clk)
2 - 65535: baud_sample