PERS_GLOB_GEN_STORAGE0 (PMU_GLOBAL) Register Description
| Register Name | PERS_GLOB_GEN_STORAGE0 |
|---|---|
| Offset Address | 0x0000000050 |
| Absolute Address | 0x00FFD80050 (PMU_GLOBAL) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Persistent Global Storage, Reg 0. |
Eight 32-bit general-purpose registers provide 256 bits of storage. Four registers are used by the FSBL and other Xilinx software products: PERS_GLOB_GEN_STORAGE{4:7}. Register is reset only by a POR reset. A system reset will not affect the persistent registers.
PERS_GLOB_GEN_STORAGE0 (PMU_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reg | 31:0 | rwNormal read/write | 0x0 | Bits [31:0] are R/W. The bits do not affect the hardware. The bits are not modified by the hardware or ROM. |