ODTMAP (DDRC) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

ODTMAP (DDRC) Register Description

Register NameODTMAP
Offset Address0x0000000244
Absolute Address 0x00FD070244 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00002211
DescriptionODT/Rank Map Register

This register is static. Static registers can only be written when the controller is in reset.

ODTMAP (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
rank1_rd_odt13:12rwNormal read/write0x2Indicates which remote ODTs must be turned on during a read from rank 1.
Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc.
For each rank, set its bit to 1 to enable its ODT.
rank1_wr_odt 9:8rwNormal read/write0x2Indicates which remote ODTs must be turned on during a write to rank 1.
Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc.
For each rank, set its bit to 1 to enable its ODT.
rank0_rd_odt 5:4rwNormal read/write0x1Indicates which remote ODTs must be turned on during a read from rank 0.
Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc.
For each rank, set its bit to 1 to enable its ODT.
rank0_wr_odt 1:0rwNormal read/write0x1Indicates which remote ODTs must be turned on during a write to rank 0.
Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc.
For each rank, set its bit to 1 to enable its ODT.