SMMU_CB7_FSYNR0 (SMMU500) Register - SMMU_CB7_FSYNR0 (SMMU500) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

SMMU_CB7_FSYNR0 (SMMU500) Register Description

Register NameSMMU_CB7_FSYNR0
Offset Address0x0000017068
Absolute Address 0x00FD817068 (SMMU_GPV)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionHolds fault syndrome information about the memory access that caused a synchronous abort exception

SMMU_CB7_FSYNR0 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
S1CBNDX19:16rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
AFR11rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
PTWF10rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
ATOF 9roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSATTR 8rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IND 6rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
PNU 5rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
WNR 4rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
PLVL 1:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details