int_q1_mask (GEM) Register Description
| Register Name | int_q1_mask |
|---|---|
| Offset Address | 0x0000000640 |
| Absolute Address |
0x00FF0B0640 (GEM0) 0x00FF0C0640 (GEM1) 0x00FF0D0640 (GEM2) 0x00FF0E0640 (GEM3) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000CE6 |
| Description | The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register. |
int_q1_mask (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:12 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| resp_not_ok_interrupt_mask | 11 | roRead-only | 0x1 | bresp/hresp not OK interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| receive_overrun_interrupt_mask | 10 | roRead-only | 0x1 | receive overrun interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| Reserved | 9:8 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| transmit_complete_interrupt_mask | 7 | roRead-only | 0x1 | transmit complete interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| amba_error_interrupt_mask | 6 | roRead-only | 0x1 | A read of this register returns the value of the AMBA (AHB/AXI) error interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| retry_limit_exceeded_or_late_collision_interrupt_mask | 5 | roRead-only | 0x1 | retry limit exceeded or late collision interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| Reserved | 4:3 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| rx_used_interrupt_mask | 2 | roRead-only | 0x1 | A read of this register returns the value of the RX Used interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| receive_complete_interrupt_mask | 1 | roRead-only | 0x1 | receive complete interrupt mask.0: Interrupt is enabled.1: Interrupt is disabled.A write to this register directly affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be generated if a 1 is written. |
| Reserved | 0 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |