enable_spi_security3 (PL390) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

enable_spi_security3 (PL390) Register Description

Register Nameenable_spi_security3
Offset Address0x0000000090
Absolute Address 0x00F9000090 (RCPU_GIC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionInterrupt Security Registers (ICDISR)

enable_spi_security3 (PL390) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
_31:0rwNormal read/write0x0Refer to the Arm Generic Interrupt Controller Architecture Specification 2.0 for a detailed register descriptions.