IOU_INTERCONNECT_ROUTE (IOU_SLCR) Register Description
| Register Name | IOU_INTERCONNECT_ROUTE |
|---|
| Offset Address | 0x0000000408 |
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| Absolute Address |
0x00FF180408 (IOU_SLCR)
|
|---|
| Width | 32 |
|---|
| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | Transaction Routing to Memory for DMA masters in IOP. |
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0: CCI bypass mode. 1: through CCI.
IOU_INTERCONNECT_ROUTE (IOU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:8 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
| NAND | 7 | rwNormal read/write | 0x0 | NAND DMA AXI read/write transaction. |
| QSPI | 6 | rwNormal read/write | 0x0 | Quad SPI DMA AXI read/write transaction. |
| SD1 | 5 | rwNormal read/write | 0x0 | SD1 DMA AXI read/write transaction. |
| SD0 | 4 | rwNormal read/write | 0x0 | SD0 DMA AXI read/write transaction. |
| GEM3 | 3 | rwNormal read/write | 0x0 | GEM3 DMA AXI read/write transaction. |
| GEM2 | 2 | rwNormal read/write | 0x0 | GEM2 DMA AXI read/write transaction. |
| GEM1 | 1 | rwNormal read/write | 0x0 | GEM1 DMA AXI read/write transaction. |
| GEM0 | 0 | rwNormal read/write | 0x0 | GEM0 DMA AXI read/write transaction. |