aes_kup_wr (CSU) Register Description
| Register Name | aes_kup_wr |
|---|---|
| Offset Address | 0x000000101C |
| Absolute Address | 0x00FFCA101C (CSU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | AES KUP Write Control |
aes_kup_wr (CSU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| iv_write | 1 | rwNormal read/write | 0x0 | When this bit is set the IV register will be written with the output of the AES. This bit can be combined with the KUP_WRITE to write the KUP and IV at the same time. The data format is {KUP0:KUP7,IV0:IV3}. All registers must be written before the key/iv will be updated. |
| kup_write | 0 | rwNormal read/write | 0x0 | When this bit is set, the output of the AES will be written into the KUP. This bit can be combined with the IV_WRITE to write the KUP and IV at the same time. All 12 registers must be written to in order to correctly set the KUP and IV values. The data must be loaded {KUP0:KUP7,IV0:IV3} |