PLL_STATUS (CRF_APB) Register - PLL_STATUS (CRF_APB) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

PLL_STATUS (CRF_APB) Register Description

Register NamePLL_STATUS
Offset Address0x0000000044
Absolute Address 0x00FD1A0044 (CRF_APB)
Width 8
TyperoRead-only
Reset Value0x00000038
DescriptionFPD PLL Clocking Status.

PLL_STATUS (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
VPLL_STABLE 5roRead-only0x1VPLL stability status.
0: not locked or bypassed.
1: locked or bypassed.
DPLL_STABLE 4roRead-only0x1DPLL stability status.
0: not locked or bypassed.
1: locked or bypassed.
APLL_STABLE 3roRead-only0x1APLL stability status.
0: not locked or bypassed.
1: locked or bypassed.
VPLL_LOCK 2roRead-only0x0VPLL
lock status.
0: not locked.
1: locked.
DPLL_LOCK 1roRead-only0x0DPLL
lock status.
0: not locked.
1: locked.
APLL_LOCK 0roRead-only0x0APLL lock status.
0: not locked.
1: locked.