SDIO_CLK_CTRL (IOU_SLCR) Register Description
| Register Name | SDIO_CLK_CTRL |
|---|---|
| Offset Address | 0x000000030C |
| Absolute Address | 0x00FF18030C (IOU_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | SD I/O Clock Control |
SDIO_CLK_CTRL (IOU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:19 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
| SDIO1_FBCLK_SEL | 18 | rwNormal read/write | 0x0 | Selection of SD Feedback clock 0: Feedback clock from MIO PAD 1: Feddback clock from EMIO |
| SDIO1_RX_SRC_SEL | 17 | rwNormal read/write | 0x0 | MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76] |
| Reserved | 16:3 | razRead as zero | 0x0 | Reserved. Writes are ignored, read data is zero. |
| SDIO0_FBCLK_SEL | 2 | rwNormal read/write | 0x0 | Selection of SD Feedback clock 0: Feedback clock from MIO PAD 1: Feddback clock from EMIO |
| SDIO0_RX_SRC_SEL | 1:0 | rwNormal read/write | 0x0 | MIO pad selection for sdio0_rx_clk (feedback clock from the PAD) 00: MIO [22] 01: MIO [38] 10: MIO [64] 11: MIO [64] |