APM1_TIMER (VCU_SLCR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

APM1_TIMER (VCU_SLCR) Register Description

Register NameAPM1_TIMER
Offset Address0x0000000204
Absolute Address 0x00A0040204 (VCU_SLCR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAPM1_TIMER

APM1_TIMER (VCU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
burst_max_val31:0rwNormal read/write0x0Maximum value of clock ticks in timing mode window in case of Mode 2. This is number of
AXI clock cycles. Timing window counter will restart once it attains the maximum value. A new timing window start after that.