MIO_PIN_45 (IOU_SLCR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MIO_PIN_45 (IOU_SLCR) Register Description

Register NameMIO_PIN_45
Offset Address0x00000000B4
Absolute Address 0x00FF1800B4 (IOU_SLCR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMIO Device Pin 45 Multiplexer Controls.

MIO_PIN_45 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8rwNormal read/write0x0reserved
L3_SEL 7:5rwNormal read/write0x0Level 3 Mux Select:
0: GPIO [45] input/output bank 1.
1: CAN1 RX input.
2: I2C1 SDA input/output.
3: FPD SWDT reset output.
4: SPI1 SS [2] output.
5: TTC1 waveform output.
6: UART1 RxD input.
7: reserved
L2_SEL 4:3rwNormal read/write0x0Level 2 Mux Select:
0: Level 3 Mux output
1: SDIO0 Data [4] input/output.
2: SDIO1 Card Detect input.
3: reserved
L1_SEL 2rwNormal read/write0x0Level 1 Mux Select:
0: Level 2 Mux output
1: reserved
L0_SEL 1rwNormal read/write0x0Level 0 Mux Select:
0: Level 1 Mux output
1: GEM1 RGMII Rx Data [0] input.
Reserved 0rwNormal read/write0x0reserved