ENABLE (GPU) Register Description
| Register Name | ENABLE |
|---|---|
| Offset Address | 0x000000101C |
| Absolute Address | 0x00FD4B101C (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Enable Register |
ENABLE (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:2 | rwNormal read/write | 0x0 | Reserved, read as zero |
| Permit_cache_read_allocate | 1 | rwNormal read/write | 0x0 | Writing a 1 to the relevant bit enables: [1] Permit_cache_read_allocate [0] Permit_cacheable_accesses |
| Permit_cacheable_accesses | 0 | rwNormal read/write | 0x0 | Writing a 1 to the relevant bit enables: [1] Permit_cache_read_allocate [0] Permit_cacheable_accesses |