ATTR_25 (PCIE_ATTRIB) Register Description
| Register Name | ATTR_25 |
|---|---|
| Offset Address | 0x0000000064 |
| Absolute Address | 0x00FD480064 (PCIE_ATTRIB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000905 |
| Description | ATTR_25 |
This register should only be written to during reset of the PCIe block
ATTR_25 (PCIE_ATTRIB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr_dev_cap2_atomicop_routing_supported | 15 | rwNormal read/write | 0x0 | Drives value on Device Capabilities2[6]. Not supported for EP. |
| attr_dev_cap2_ari_forwarding_supported | 14 | rwNormal read/write | 0x0 | Drives value on Device Capabilities2[5]. Not supported for EP. |
| attr_cpl_timeout_ranges_supported | 13:10 | rwNormal read/write | 0x2 | Supported range of completion timeouts. Drives Device Capability 2 [3:0] |
| attr_cpl_timeout_disable_supported | 9 | rwNormal read/write | 0x0 | If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root ports. Drives Device Capability 2 [4] |
| attr_cmd_intx_implemented | 8 | rwNormal read/write | 0x1 | INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0. |
| attr_class_code | 7:0 | rwNormal read/write | 0x5 | Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register. |