DMA_system_address0_register (NAND) Register Description
| Register Name | DMA_system_address0_register |
|---|---|
| Offset Address | 0x0000000050 |
| Absolute Address | 0x00FF100050 (NAND) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | DMA System Address, reg2. |
Applies only to MDMA transaction mode.
DMA_system_address0_register (NAND) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| DMA_system_address0_register | 31:0 | rwNormal read/write | 0x0 | System memory address for a DMA transfer. Applicable to MDMA mode of transaction. Contains the LSB address when using 64-bit addressing with the DMA_system_address1_register. The driver initializes this register before starting a DMA transaction. The DMA transfer waits at every boundary specified by the DMA_buffer_boundary_register. The controller generates the DMA interrupt to request an update to the address register(s). The driver sets the next system address of the next data position. |