INIT3_SHADOW (DDRC) Register Description
| Register Name | INIT3_SHADOW |
|---|---|
| Offset Address | 0x00000020DC |
| Absolute Address | 0x00FD0720DC (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000510 |
| Description | SDRAM Initialization Shadow Register 3 |
All register fields are quasi-dynamic group 1, unless described otherwise in the register field description. Group 1 registers can be written when no read/write traffic is present at the DFI.
INIT3_SHADOW (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| mr | 31:16 | rwNormal read/write | 0x0 | DDR3/DDR4: Value loaded into MR0 register. LPDDR3/LPDDR4 - Value to write to MR1 register Programming Mode: Quasi-dynamic Group 1 and Group 4 |
| emr | 15:0 | rwNormal read/write | 0x510 | DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by the DDRC during write leveling. LPDDR3/LPDDR4 - Value to write to MR2 register |