SMMU_CB5_PMINTENCLR (SMMU500) Register Description
| Register Name | SMMU_CB5_PMINTENCLR |
|---|---|
| Offset Address | 0x0000015F4C |
| Absolute Address | 0x00FD815F4C (SMMU_GPV) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | Provides the equivalent of the PMINTENCLRx in the register map of a translation context bank. Disables the generation of interrupt requests on overflows from each implemented event counter. |
SMMU_CB5_PMINTENCLR (SMMU500) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| P3 | 3 | woWrite-only | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
| P2 | 2 | woWrite-only | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
| P1 | 1 | woWrite-only | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
| P0 | 0 | woWrite-only | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |