PIDR3 (STM) Register Description
| Register Name | PIDR3 |
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| Offset Address | 0x0000000FEC |
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| Absolute Address |
0x00FE9C0FEC (CORESIGHT_SOC_STM)
|
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| Width | 32 |
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| Type | roRead-only |
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| Reset Value | 0x00000000 |
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| Description | PID - RevAnd and Customer-modified Bit Fields. |
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Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer_Modified bit fields.
PIDR3 (STM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| REVAND | 7:4 | roRead-only | 0x0 | Indicates minor errata fixes specific to the design, for example metal fixes after implementation. In most cases this field is zero. Arm recommendeds that the component designers ensure that the bit field can be changed by a metal fix if required, for example by driving the bit field from registers that reset to zero. |
| CMOD | 3:0 | roRead-only | 0x0 | Where the component is reusable IP, this value indicates if the customer has modified the behavior of the component. In most cases this field is zero. |