MASK_DATA_3_MSW (GPIO) Register Description
| Register Name | MASK_DATA_3_MSW |
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| Offset Address | 0x000000001C |
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| Absolute Address |
0x00FF0A001C (GPIO)
|
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | Maskable Output Data (GPIO Bank3, EMIO, Upper 16bits) |
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This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the upper 16 bits of bank3, which corresponds to EMIO[31:16].
MASK_DATA_3_MSW (GPIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
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| MASK_3_MSW | 31:16 | woWrite-only | 0x0 | Operation is the same as MASK_DATA_0_LSW [MASK_0_LSW] |
| DATA_3_MSW | 15:0 | rwNormal read/write | 0x0 | Operation is the same as MASK_DATA_0_LSW [DATA_0_LSW] |