GICP2_IRQ_MASK (LPD_SLCR) Register Description
| Register Name | GICP2_IRQ_MASK |
|---|---|
| Offset Address | 0x000000802C |
| Absolute Address | 0x00FF41802C (LPD_SLCR) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0xFFFFFFFF |
| Description | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
GICP2_IRQ_MASK (LPD_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| src31 | 31 | roRead-only | 0x1 | Bit 6 of PL_PS IRQ0. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src30 | 30 | roRead-only | 0x1 | Bit 5 of PL_PS IRQ0. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src29 | 29 | roRead-only | 0x1 | Bit 4 of PL_PS IRQ0. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src28 | 28 | roRead-only | 0x1 | Bit 3 of PL_PS IRQ0. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src27 | 27 | roRead-only | 0x1 | Bit 2 of PL_PS IRQ0. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src26 | 26 | roRead-only | 0x1 | Bit 1 of PL_PS IRQ0. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src25 | 25 | roRead-only | 0x1 | Bit 0 of PL_PS IRQ0. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for. |
| src24 | 24 | roRead-only | 0x1 | XMPUs error interrupt for LPD |
| src23 | 23 | roRead-only | 0x1 | EFUSE interrupt |
| src22 | 22 | roRead-only | 0x1 | DMA for CSU interrupt |
| src21 | 21 | roRead-only | 0x1 | Device Configuration Module Interrupt |
| src20 | 20 | roRead-only | 0x1 | LPD DMA interrupt for channel 7 |
| src19 | 19 | roRead-only | 0x1 | LPD DMA interrupt for channel 6 |
| src18 | 18 | roRead-only | 0x1 | LPD DMA interrupt for channel 5 |
| src17 | 17 | roRead-only | 0x1 | LPD DMA interrupt for channel 4 |
| src16 | 16 | roRead-only | 0x1 | LPD DMA interrupt for channel 3 |
| src15 | 15 | roRead-only | 0x1 | LPD DMA interrupt for channel 2 |
| src14 | 14 | roRead-only | 0x1 | LPD DMA interrupt for channel 1 |
| src13 | 13 | roRead-only | 0x1 | LPD DMA interrupt for channel 0 (ADMA) |
| src12 | 12 | roRead-only | 0x1 | Wakeup from USB3_1 to PMU |
| src11 | 11 | roRead-only | 0x1 | Wakeup from USB3_0 to PMU |
| src10 | 10 | roRead-only | 0x1 | USB3_1 OTG interrupt |
| src9 | 9 | roRead-only | 0x1 | USB3_1 Endpoint related interrupts. Interrupt for Control type |
| src8 | 8 | roRead-only | 0x1 | USB3_1 Endpoint related interrupts. |
| src7 | 7 | roRead-only | 0x1 | USB3_1 Endpoint related interrupts. Interrupt for Isochronous |
| src6 | 6 | roRead-only | 0x1 | USB3_1 Endpoint related interrupts. Interrupt for Bulk |
| src5 | 5 | roRead-only | 0x1 | USB3_0 OTG interrupt |
| src4 | 4 | roRead-only | 0x1 | USB3_0 Endpoint related interrupts. Interrupt for Control type |
| src3 | 3 | roRead-only | 0x1 | USB3_0 Endpoint related interrupts. |
| src2 | 2 | roRead-only | 0x1 | USB3_0 Endpoint related interrupts. Interrupt for Isochronous |
| src1 | 1 | roRead-only | 0x1 | USB3_0 Endpoint related interrupts. Interrupt for Bulk |
| src0 | 0 | roRead-only | 0x1 | Gigabit Ethernet3 wakeup interrupt |