REQ_PWRUP_INT_EN (PMU_GLOBAL) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

REQ_PWRUP_INT_EN (PMU_GLOBAL) Register Description

Register NameREQ_PWRUP_INT_EN
Offset Address0x0000000118
Absolute Address 0x00FFD80118 (PMU_GLOBAL)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionPower-up Request; Interrupt Enable.

0: no effect. 1: enable interrupt (sets mask = 0). Write-only.

REQ_PWRUP_INT_EN (PMU_GLOBAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PL23woWrite-only0x0Programmable Logic, PL. Controlled by external FET via MIO pin. This optional control uses MIO [32] and is equivalent to PMU signal [6].
FP22woWrite-only0x0Full-power Domain, FPD. Controlled by external FET via MIO pin. This optional control uses MIO [31] and is equivalent to PMU signal [5].
USB121woWrite-only0x0USB controller 1.
USB020woWrite-only0x0USB controller 0.
OCM_Bank319woWrite-only0x0OCM Bank 3.
OCM_Bank218woWrite-only0x0OCM Bank 2.
OCM_Bank117woWrite-only0x0OCM Bank 1.
OCM_Bank016woWrite-only0x0OCM Bank 0.
TCM1B15woWrite-only0x0RPU core 1, TCM_B.
TCM1A14woWrite-only0x0RPU core 1, TCM_A.
TCM0B13woWrite-only0x0RPU core 0, TCM_B.
TCM0A12woWrite-only0x0RPU core 0, TCM_A.
RPU10woWrite-only0x0RPU processors.
L2_Bank0 7woWrite-only0x0APU L2 Cache.
PP1 5woWrite-only0x0GPU Pixel Processor 1.
PP0 4woWrite-only0x0GPU Pixel Processor 0.
ACPU3 3woWrite-only0x0APU core 3.
ACPU2 2woWrite-only0x0APU core 2.
ACPU1 1woWrite-only0x0APU core 1.
ACPU0 0woWrite-only0x0APU core 0.