L3_PLL_FBDIV_FRAC_3_MSB (SERDES) Register Description
| Register Name | L3_PLL_FBDIV_FRAC_3_MSB |
|---|---|
| Offset Address | 0x000000E360 |
| Absolute Address | 0x00FD40E360 (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register value is generated by Vivado PCW. |
L3_PLL_FBDIV_FRAC_3_MSB (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PLL_FBDIV_FRAC_3_MSB_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| pll_fbdiv_frac_3_msv_rsvd | 7 | roRead-only | 0x0 | Value generated by PCW. |
| tm_force_en_frac | 6 | rwNormal read/write | 0x0 | Value generated by PCW. |
| tm_en_frac | 5 | rwNormal read/write | 0x0 | Value generated by PCW. |
| fbdiv_frac_3_msb_rsvd | 4:3 | roRead-only | 0x0 | Value generated by PCW. |
| fbdiv_frac_3_msb | 2:0 | rwNormal read/write | 0x0 | Value generated by PCW. |