ADDR_ERROR_INT_DIS (RTC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ADDR_ERROR_INT_DIS (RTC) Register Description

Register NameADDR_ERROR_INT_DIS
Offset Address0x000000003C
Absolute Address 0x00FFA6003C (RTC)
Width 1
TypewoWrite-only
Reset Value0x00000000
DescriptionAddress Decode Error Interrupt Disable.

A write to the register bit will mask the Address Decode Error interrupt. 0: ignored. 1: set the ADDR_ERROR_INT_MASK = 1.

ADDR_ERROR_INT_DIS (RTC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Mask 0woWrite-only0x0Mask for an address decode error interrupt