PIDR1 (A53_PMU_0) Register Description
| Register Name | PIDR1 |
|---|---|
| Offset Address | 0x0000000FE4 |
| Absolute Address | 0x00FEC30FE4 (CORESIGHT_A53_PMU_0) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x000000B9 |
| Description | Performance Monitors Peripheral Identification Register 1 |
PIDR1 (A53_PMU_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| DES_0 | 7:4 | roRead-only | 0xB | Designer, least significant nibble of JEP106 ID code. For Arm Limited, this field is 0b1011. |
| PART_1 | 3:0 | roRead-only | 0x9 | Part number, most significant nibble. |