GICP_PMU_IRQ_ENABLE (LPD_SLCR) Register Description
Register Name | GICP_PMU_IRQ_ENABLE |
---|---|
Offset Address | 0x00000080A8 |
Absolute Address | 0x00FF4180A8 (LPD_SLCR) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
GICP_PMU_IRQ_ENABLE (LPD_SLCR) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:8 | razRead as zero | 0x0 | Reserved for future use |
src4 | 4 | woWrite-only | 0x0 | Create single interrupt source for PMU from GICP4 |
src3 | 3 | woWrite-only | 0x0 | Create single interrupt source for PMU from GICP3 |
src2 | 2 | woWrite-only | 0x0 | Create single interrupt source for PMU from GICP2 |
src1 | 1 | woWrite-only | 0x0 | Create single interrupt source for PMU from GICP1 |
src0 | 0 | woWrite-only | 0x0 | Create single interrupt source for PMU from GICP0 |