IDR (SPI) Register Description
| Register Name | IDR |
|---|---|
| Offset Address | 0x000000000C |
| Absolute Address |
0x00FF04000C (SPI0) 0x00FF05000C (SPI1) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Interrupt disable |
0: no effect. 1: disable interrupt.
IDR (SPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:7 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| TX_FIFO_underflow | 6 | woWrite-only | 0x0 | TX FIFO underflow enable |
| RX_FIFO_full | 5 | woWrite-only | 0x0 | RX FIFO full enable |
| RX_FIFO_not_empty | 4 | woWrite-only | 0x0 | RX FIFO not empty enable |
| TX_FIFO_full | 3 | woWrite-only | 0x0 | TX FIFO full enable |
| TX_FIFO_not_full | 2 | woWrite-only | 0x0 | TX FIFO not full enable |
| MODE_FAIL | 1 | woWrite-only | 0x0 | ModeFail interrupt enable |
| RX_OVERFLOW | 0 | woWrite-only | 0x0 | Receive Overflow interrupt enable |