PMCGSMR4 (SMMU500) Register Description
Register Name | PMCGSMR4 |
---|---|
Offset Address | 0x0000003A10 |
Absolute Address | 0x00FD803A10 (SMMU_GPV) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Specifies StreamID filtering of the events counted in a Counter group |
PMCGSMR4 (SMMU500) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
MASK | 25:16 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
ID | 9:0 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |