GP_CONTR_REG_VSCL_INITIAL_ADDR (GPU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GP_CONTR_REG_VSCL_INITIAL_ADDR (GPU) Register Description

Register NameGP_CONTR_REG_VSCL_INITIAL_ADDR
Offset Address0x0000000080
Absolute Address 0x00FD4B0080 (GPU)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionGP Control Register VSCL Initial Address

GP_CONTR_REG_VSCL_INITIAL_ADDR (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
GP_CONTR_REG_VSCL_INITIAL_ADDR31:3roRead-only0x0Start address of vertex shader command list
Reserved 2:0roRead-only0x0Reserved, write as zero, read undefined