PIT3_CONTROL (PMU_IOMODULE) Register Description
| Register Name | PIT3_CONTROL |
|---|---|
| Offset Address | 0x0000000078 |
| Absolute Address | 0x00FFD40078 (PMU_IOMODULE) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | PIT3 Control Register |
The EN bit in this register enables/disables counting. The PRELOAD bit determines if the counting is continuous with automatic reload of the PIT3_PRELOAD value when lapsing (PIT3_COUNTER = 0) or if the counting is stopped after counting the number of cycles defined in PIT3_PRELOAD.
PIT3_CONTROL (PMU_IOMODULE) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:2 | razRead as zero | 0x0 | reserved |
| PRELOAD | 1 | woWrite-only | 0x0 | 0 = Counter counts PIT3_PRELOAD value cycles and then stops 1 = Counter value is automatically reloaded with the PIT3_PRELOAD value when counter lapses |
| EN | 0 | woWrite-only | 0x0 | 0 = Counter Disabled 1 = Counter Enabled |