PMCGCR0 (SMMU500) Register - PMCGCR0 (SMMU500) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

PMCGCR0 (SMMU500) Register Description

Register NamePMCGCR0
Offset Address0x0000003800
Absolute Address 0x00FD803800 (SMMU_GPV)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x04000000
DescriptionControls Counter group behavior.

PMCGCR0 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CGNC27:24roRead-only0x4Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SIDG22:16roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
X12rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
E11rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
CBAEN10rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TCEFCFG 9:8rwNormal read/write0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NDX 3:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details