PMCGCR0 (SMMU500) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

PMCGCR0 (SMMU500) Register Description

Register Name	PMCGCR0
Offset Address	0x0000003800
Absolute Address	0x00FD803800 (SMMU_GPV)
Width	32
Type	mixedMixed types. See bit-field details.
Reset Value	0x04000000
Description	Controls Counter group behavior.

PMCGCR0 (SMMU500) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
CGNC	27:24	roRead-only	0x4	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SIDG	22:16	roRead-only	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
X	12	rwNormal read/write	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
E	11	rwNormal read/write	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
CBAEN	10	rwNormal read/write	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TCEFCFG	9:8	rwNormal read/write	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NDX	3:0	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details