ATTR_92 (PCIE_ATTRIB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ATTR_92 (PCIE_ATTRIB) Register Description

Register NameATTR_92
Offset Address0x0000000170
Absolute Address 0x00FD480170 (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionATTR_92

This register should only be written to during reset of the PCIe block

ATTR_92 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_ll_ack_timeout_func 1:0rwNormal read/write0x0Defines how LL_ACK_TIMEOUT is to be used, if enabled with LL_ACK_TIMEOUT_EN (otherwise, this is not used).
0 = Absolute Value on LL_ACK_TIMEOUT
1 = Add LL_ACK_TIMEOUT to the built-in table value
2 = Subtract LL_ACK_TIMEOUT from the built-in table value
It is the users responsibility to ensure that if "1" is chosen, the timeout value does not overflow the 15-bit field. The core will prevent underflows if option "2" is chosen (final value will be 0 for that case).