CONFIG_0 (APU) Register Description
| Register Name | CONFIG_0 |
|---|---|
| Offset Address | 0x0000000020 |
| Absolute Address | 0x00FD5C0020 (APU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000F0F |
| Description | CPU Core Configuration |
CONFIG_0 (APU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| CFGTE | 27:24 | rwNormal read/write | 0x0 | Set instruction set for exception handling. Only change this signal when the core is in the reset state. |
| CFGEND | 19:16 | rwNormal read/write | 0x0 | Set data endiannes during exception handling. Only change this signal when the core is in the reset state. |
| VINITHI | 11:8 | rwNormal read/write | 0xF | Set exception vector locations. Only change this signal when the core is in the reset state. |
| AA64nAA32 | 3:0 | rwNormal read/write | 0xF | Set register width state (1=64bit, 0=32bit) at cold reset. Only change when the core is in the reset state. |