Interrupt_Status (I2C) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Interrupt_Status (I2C) Register Description

Register NameInterrupt_Status
Offset Address0x0000000010
Absolute Address 0x00FF020010 (I2C0)
0x00FF030010 (I2C1)
Width16
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionIIC interrupt status register

Interrupt_Status (I2C) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved15:10wtcReadable, write a 1 to clear0x0Reserved, read as zero, ignored on write.
ARB_LOST 9wtcReadable, write a 1 to clear0x0arbitration lost
1 = master loses bus ownership during a transfer due to ongoing arbitration
Reserved 8wtcReadable, write a 1 to clear0x0Reserved, read as zero, ignored on write.
RX_UNF 7wtcReadable, write a 1 to clear0x0FIFO receive underflow
1 = host attempts to read from the I2C data register more times than the value of the transfer size register plus one
TX_OVF 6wtcReadable, write a 1 to clear0x0FIFO transmit overflow
1 = host attempts to write to the I2C data register more times than the FIFO depth
RX_OVF 5wtcReadable, write a 1 to clear0x0Receive overflow
1 = This bit is set whenever FIFO is full and a new byte is received. The new byte is not acknowledged and contents of the FIFO remains unchanged.
SLV_RDY 4wtcReadable, write a 1 to clear0x0Monitored slave ready
1 =
addressed slave returns ACK.
TO 3wtcReadable, write a 1 to clear0x0Transfer time out
1 =
I2C sclk line is kept low for longer time
NACK 2wtcReadable, write a 1 to clear0x0Transfer not acknowledged
1 = slave responds with a NACK or master terminates the transfer before all data is supplied
DATA 1wtcReadable, write a 1 to clear0x0More data
1 =
Data being sent or received
COMP 0wtcReadable, write a 1 to clear0x0Transfer complete
1 =
transfer is complete