SMMU_TLBIVMID (SMMU500) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SMMU_TLBIVMID (SMMU500) Register Description

Register NameSMMU_TLBIVMID
Offset Address0x0000000064
Absolute Address 0x00FD800064 (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionInvalidates all Non-secure non-Hyp TLB entries having the specified VMID.

SMMU_TLBIVMID (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
VMID 7:0woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details