GQSPI_FIFO_CTRL (QSPI) Register Description
| Register Name | GQSPI_FIFO_CTRL |
|---|---|
| Offset Address | 0x000000014C |
| Absolute Address | 0x00FF0F014C (QSPI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | GQSPI FIFO Control |
Software Driver name: XGQSPIPS_FIFO_CTRL
GQSPI_FIFO_CTRL (QSPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:3 | razRead as zero | 0x0 | reserved |
| RST_RX_FIFO | 2 | woWrite-only | 0x0 | Reset Receive FIFO: Software Driver name: XGQSPIPS_RST_RX_FIFO 0: Do not clear Receive FIFO Contents 1: Reset Receive FIFO contents Do not use RST_RX_FIFO while controller is actively transmitting/receiving data to/from Flash device. This bit should be used only when GQSPI is in IO mode (GQSPI_CFG.MODE_EN=0x0). Switch to IO mode if operating in DMA Mode. After RST_RX_FIFO bit is written, Controller takes few clock cycles to update the RX_FIFO_Empty status bit. Software can read the RX_FIFO_empty bit twice to allow enough time for the controller to update the status bit. |
| RST_TX_FIFO | 1 | woWrite-only | 0x0 | Reset Transmit FIFO: Software Driver name: XGQSPIPS_RST_TX_FIFO 0: Do not clear Transmit FIFO Contents 1: Reset Transmit FIFO contents Do not use RST_TX_FIFO while controller is actively transmitting/receiving data to/from Flash device. After RST_TX_FIFO bit is written, Controller takes few clock cycles to update the TX_FIFO_Empty status bit. Software can read the TX_FIFO_empty bit twice to allow enough time for the controller to update the status bit. |
| RST_GEN_FIFO | 0 | woWrite-only | 0x0 | Reset Generic FIFO: Software Driver name: XGQSPIPS_RST_GEN_FIFO 0: Do not clear Generic FIFO Contents 1: Reset Generic FIFO contents Do not use RST_GEN_FIFO while controller is actively transmitting/receiving data to/from Flash device. After RST_GEN_FIFO bit is written, Controller takes few clock cycles to update the Gen_FIFO_Empty status bit. Software can read the Gen_FIFO_empty bit twice to allow enough time for the controller to update the status bit. |