QSPIDMA_DST_I_MASK (QSPI) Register Description
| Register Name | QSPIDMA_DST_I_MASK |
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| Offset Address | 0x0000000820 |
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| Absolute Address |
0x00FF0F0820 (QSPI)
|
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x000000FE |
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| Description | DST DMA Interrupt Mask |
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Reads will return the status of the interrupt mask - 1 indicates mask the interrupt, do not pass it along - 0 indicates do not mask the interrupt, pass it along as is. Writes to this register are ignored.
QSPIDMA_DST_I_MASK (QSPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:8 | razRead as zero | 0x0 | reserved |
| FIFO_OVERFLOW | 7 | roRead-only | 0x1 | DST FIFO Overflow. |
| INVALID_APB | 6 | roRead-only | 0x1 | APB Address Decode Error. |
| THRESH_HIT | 5 | roRead-only | 0x1 | DST FIFO Reached Watermark Value. |
| TIMEOUT_MEM | 4 | roRead-only | 0x1 | Timeout Counter #1 Expired. |
| TIMEOUT_STRM | 3 | roRead-only | 0x1 | Timeout Counter #2 Expired. |
| AXI_BRESP_ERR | 2 | roRead-only | 0x1 | AXI Memory Write Command Error. |
| DONE | 1 | roRead-only | 0x1 | DMA Completed Write Command. |
| Reserved | 0 | razRead as zero | 0x0 | reserved |