RX_thres_REG (QSPI) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

RX_thres_REG (QSPI) Register Description

Register NameRX_thres_REG
Offset Address0x000000002C
Absolute Address 0x00FF0F002C (QSPI)
Width32
TyperwNormal read/write
Reset Value0x00000001
DescriptionRX FIFO Threshold

RX_thres_REG (QSPI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Threshold_of_RX_FIFO31:0rwNormal read/write0x1Defines the level at which the RX FIFO not empty interrupt is generated
Note: Change this value only when controller is not communicating with the memory device.